Device and method for compensating for voltage drops

ABSTRACT

A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

FIELD OF THE INVENTION

The present invention relates to devices and methods for compensatingfor voltage drops within an integrated circuit.

BACKGROUND OF THE INVENTION

Modern integrated circuits are required to operate in very highfrequencies while consuming a relatively limited amount of voltage. Inorder to reduce the power consumption of modern integrated circuits thelevel of supply voltage has dramatically decreased during the lastdecade.

This supply voltage reduction has some drawbacks such as an increasedsensitivity to voltage drops (also referred to as IR drops or droops)that are proportional to the current (I) consumed by the integratedcircuit and to the resistance (R) of the conductors that are connectedto the integrated circuit as well as to conductors that are locatedinside the integrated circuit.

A voltage drop reduces the voltage that is provided to internalcomponents of the integrated circuit and thus can temporarily preventthe integrated circuit from operating in a proper manner.

U.S. Pat. No. 6,058,257 of Nojima, and U.S. patent applicationpublication number 2004/0238850 of Kusumoto, both being incorporatedherein by reference, describe apparatuses, devices and methods fordesigning an integrated circuit such as to reduce internal voltagedrops.

U.S. patent application publication number 2004/0030511 of Tien et al.,being incorporated herein by reference, describes a method forevaluating (by using simulations) voltage drops.

U.S. patent application 2004/0049752 of Iwanishi et al., beingincorporated herein by reference, describes an integrated circuit designprocess that is responsive to voltage drops.

Japanese patent application JP05021738 titled “A semiconductorintegrated circuit”, being incorporated herein by reference, describesan apparatus that increases the supply voltage by a predetermined amountand during a predefined period once a certain event is detected.

U.S. Pat. Nos. 6,044,639 and 6,538,497, being incorporated herein byreference, illustrate various prior art devices and methods forcompensating for IR drops.

There is a need to provide a device and method for efficientlycompensating for voltage drops.

SUMMARY OF THE PRESENT INVENTION

A device and a method for compensating for voltage drops, as describedin the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates a device, according to an embodiment of theinvention;

FIG. 2 illustrates various portions of an integrated circuit, accordingto an embodiment of the invention;

FIG. 3 is a schematic electric diagram of a compensation circuit as wellas various equivalent components according to an embodiment of theinvention;

FIG. 4 is a schematic electric diagram of a compensation circuit as wellas various equivalent components according to another embodiment of theinvention;

FIG. 5 is a schematic electric diagram of a two compensation circuits, aselection circuit and various equivalent components according to anembodiment of the invention;

FIG. 6 illustrates a peak detector and a timeout circuit, according toan embodiment of the invention;

FIG. 7 illustrates a voltage sampling circuit, according to anembodiment of the invention;

FIG. 8 illustrates voltage drop and the result of two voltage dropcompensation measures, according to an embodiment of the invention;

FIG. 9 is a flow chart of a method for compensating for voltage dropsaccording to an embodiment of the invention; and

FIG. 10 is a flow chart of a method for compensating for voltage dropsaccording to an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following figures illustrate exemplary embodiments of the invention.They are not intended to limit the scope of the invention but ratherassist in understanding some of the embodiments of the invention. It isfurther noted that all the figures are out of scale.

According to various embodiments of the invention a method and devicefor compensating for voltage drops are provided. The compensation caninvolve comparing the voltage at a sensing point to a maximal voltagelevel (also referred to as peak voltage level) measured at this sensingpoint and increasing the voltage of that point when a voltage drop isdetected. Conveniently, the peak voltage level represents the maximalvalue of the voltage at the sensing point within a peak measurementperiod. Conveniently, the detection and voltage increment are relativelyfast, in comparison to the development of the IR drop and especially inrelation to a response period of an external voltage supply unit.

According to an embodiment of the invention the compensation can involveapplying a fast compensation scheme (that can involve using internalcomponents of the integrated circuit) as well as applying a slowercompensation scheme that can involve adjusting a supply voltage suppliedby a voltage supply unit in response to sampled voltages derived fromthe voltage at the sensing point.

Conveniently, the compensation circuit uses an I/O type transistor as aswitch that can be opened such as to provide current from anothervoltage supply that is used for additional purposes and provides asecond supply voltage that is higher then the first supply voltage.

Conveniently, multiple sensing points are defined within an integratedcircuit and each sensing point can be connected to its own compensationcircuit, and/or to a feedback path towards the voltage supply unit.

According to various embodiments of the invention the peak voltage levelis a maximal level of a voltage at a sensing point. The peak voltagelevel can be detected during a peak measurement period. The period canbe a fixed period or can vary. Conveniently, the voltage peak level at acertain time represents the maximal voltage level within a predefinedtime window that ends at that certain time. This technique can bereferred to as a sliding window technique.

According to an embodiment of the invention the compensation circuitincludes a timeout circuit that terminates any voltage increment after apredefined timeout period expires. This timeout period can correspond toa response period of the feedback loop and the voltage supply unit.

Conveniently, the method and device can be implemented by using standardcomponents such as a I/O type transistor, as well as make use of a I/Ovoltage supply unit that is used to supply a supply voltage to I/O padsused for interfacing an integrated circuit to external world.

Conveniently the method includes: (i) providing at least a first supplyvoltage to an integrated circuit; (ii) comparing between a voltage levelat a sensing point within an integrated circuit to a reference voltagederived from a voltage peak level, at the sensing point; and (iii)selectively increasing the voltage at the sensing point in response tothe comparison.

Conveniently, a device is provided. The device can include at least onecurrent consuming component (such as but not limited to a core or amemory or peripheral unit). The device also includes a compensationcircuit that is adapted to compare between a voltage level at a sensingpoint within an integrated circuit and between a reference voltagederived from a voltage peak level at the sensing point; and toselectively increase the voltage at the sensing point in response to thecomparison.

FIG. 1 illustrates a device 10, according to an embodiment of theinvention. Device 20 can include one or more integrated circuits, andcan include one or more voltage supply units, can be a mobile devicesuch as but not limited to a cellular phone, a laptop computer, apersonal data accessory and the like. For convenience of explanationonly a first voltage supply unit 44, a second voltage supply unit 48 anda single integrated circuit 20 are illustrated.

The first voltage supply unit 44 provides a first supply voltage Vcc 45while the second voltage supply unit provides a higher supply voltage Vh49. Conveniently Vh 49 is supplied to various I/O ports and/orperipherals such as peripherals 26 of FIG. 2.

The first voltage supply unit 44 can include regulating elements,voltage limiting circuitry, and the like. It conveniently includes avoltage adjustment unit that can be responsive to feedback signalsprovided from the integrated circuit 20. The first voltage supply unit44 usually includes smoothing components such as filters and/orcapacitors that smooth the first supply voltage Vcc 45. The firstvoltage supply unit 44 can receive feedback from the integrated circuit20 and accordingly alter the first supply voltage Vcc that is providedto the integrated circuit 20. The adjustment period is usually long,thus one or more compensation circuits (such as circuit 90 of FIG. 3) isincluded within integrated circuit 20. Conveniently, once (or shortlyafter) an adjusted first supply voltage ends is provided to theintegrated circuit 20 the compensation circuit 90 can cease tocompensate for the voltage drop.

FIG. 2 illustrates various portions of an integrated circuit 20,according to an embodiment of the invention.

Integrated circuit 20 includes a first supply voltage network such asbut not limited to first grid 22 and a second supply voltage networksuch as but not limited to a second grid 21. It also includes multiplecomponents such as cores 24 and 24′, peripherals (I/O pads etc.) 26 andmemory units 28 and 28′. The first voltage supply grid 22 is connectedto one or more pins 61. The second voltage supply grid 21 is connectedto one or more pins 62. Pins 61 are connected to the first voltagesupply unit 44 while pins 62 are connected to the second voltage supplygrid 21. It is noted that the voltage supply grid is also referred to asa power grid or supply grid.

The first power supply grid 22 is connected to core 24, core 24′, memoryunit 28 and memory unit 28′. The second power supply grid 21 isconnected to peripherals 26. It is noted that at least one component canbe fed by both power grids, but this is not necessarily so.

Two exemplary, non-limiting and out of scale sensing points 32 and 32′are also illustrated. Sensing point 32 is positioned within the area ofcore 24 while sensing point 32′ is located within core 24′. It is notedthat much more than a pair of sensing points can be defined withinintegrated circuit 20. It is further noted that sensing points can belocated within other components of the integrated circuit 20 as well asbetween components of the integrated circuit 20.

Internal voltage drops are formed when one or more of these componentsconsumes current, and especially when such a component consumes asubstantial amount of current. Such a current consumption is usuallyassociated with complex computational tasks, memory transfer bursts andthe like.

The multiple sensing points are selected such as to measure thesesubstantial voltage drops. The selection is usually based upon asimulation of the integrated circuit. Designers are usually well awareof the possible current consuming components. Typically, more than asingle sensing point is positioned near a single core. In addition, atleast one sensing point can be located in substantially the center ofthe integrated circuit, or in locations that are relatively far frompins 61 and 62.

FIG. 3 is a schematic electric diagram of a compensation circuit 90 aswell as various equivalent components 53-65 and 93, according to anembodiment of the invention.

FIG. 3 illustrates various components such as power transistor. 92, peakdetector 70, timeout circuit 78, comparator 80, pins 61 and 62 and firstand second voltage supply units 44 and 48.

FIG. 3 also illustrates equivalent components that represent theresistance (represented by resistors 53, 63 and 93), capacitances(represented by capacitors 52 and 64) and current consumption(represented by current drain 65) of various components as well asconductors of the integrated circuit and various conductors connected tothe first and second voltage supply units 44 and 48.

Resistor 53 represents the impedance of the interconnect lines(conductors) between the first voltage supply unit 44 and one or morepins 61 of integrated circuit 20. Capacitor 52 represents thecapacitance of these conductors as well as an output capacitance of thefirst voltage supply unit 44, as viewed from one or more pins 61 ofintegrated circuit 20.

Resistor 63 represents the resistance of the first voltage supply grid22 between pin 61 and sensing point 32. Resistor 93 represents theresistance of the second voltage supply grid 21 between pin 62 andsensing point 32. Capacitor 64 represents the equivalent capacitance ofthe integrated circuit as viewed from sensing point 32. Current sink 65represents the current consumption of one or more components ofintegrated circuit 20, as viewed from sensing point 32.

The peak detector 70 detects the maximal value of the voltage at sensingpoint 32. This maximal value is measured during a peak measurementperiod. The peak detector is connected to a timeout circuit 78 that iscapable of stopping a voltage compensation period after a timeout periodexpires.

Conveniently the timeout circuit 78 outputs a reference voltage that isresponsive to the peak voltage level. Conveniently the reference voltagegenerated by the peak detector 70 is gradually decremented so that thevoltage compensation session stops after a predefined timeout period.Resistor 53 is connected between the first voltage supply unit 44 andpin 61. Capacitor 52 is connected between the ground and pin 61.Resistor 63 is connected between pin 61 and sensing point 32. Sensingpoint 32 is also connected to a first end of current drain 65, to afirst end of capacitor 64, to a drain of PMOS 92, to a non-invertinginput 81 of comparator 80 and to an input of peak detector 70.

The other end of capacitor 64 and current drain 65 are grounded. Theoutput of peak detector 70 is connected to an input of timeout circuit78. The output of timeout circuit 78 is connected to an inverting input83 of comparator 80. The output 85 of comparator 80 is connected to agate of power transistor 92 so that it opens PMOS 92 when a voltage dropis detected. The source of PMOS 92 is connected, via resistor 93 and pin62 to the second supply unit 48.

PMOS 92, comparator 80, peak detector 70 and timeout circuit 78 form acompensation circuit 90. This circuit is characterized by a fastresponse period, in comparison to the development of the voltage (IR)drop evolution and especially in relation to a response period of thefirst voltage supply unit 44. It is noted that slow compensationcircuits can also be used, but a gap resulting from their slow responsecan require to supply a higher first supply voltage or to hamper theperformance of integrated circuit 20.

For simplicity of explanation the equivalent capacitance and resistanceof the second power supply unit 48 as well as the resistance andcapacitance of connectors that connect it to pin 62 are not shown.

Conveniently, multiple sensing points can be connected to one or morecurrent consuming components of integrated circuit 20, such as cores 24and 24′.

When core 24 consumes more current (the current drained by current drain65 increases) the voltage at the sensing point 32 decreases due to avoltage that is developed over resistors 63 and 53 and due to adischarge of capacitor 64. It is assumed that because of this voltagedrop the reference voltage provided to the inverting input 83 ofcomparator 80 is higher then the voltage provided to the non-invertinginput 81 of comparator 80. In response, comparator 80 opens PMOS 92 thatprovides a current from the second voltage supply unit 48. This currentslows down or stops the discharge of capacitor 64 and can even chargeit. When the core 24 reduces its current consumption or the capacitor 64is charged back to its initial voltage (within a detectable voltageerror). FIG. 4 is a schematic electric diagram of a compensation circuit90 as well as various equivalent components according to anotherembodiment of the invention. The circuit illustrated in FIG. 4 differsfrom the circuit of FIG. 3 by including a feedback path 62 fromintegrated circuit 20 to the first voltage supply unit 44. The feedbackpath 62 usually includes a sampling unit (such as sampling unit 30 ofFIG. 7) and one or more conductors. The sampling unit can send analogsignals and/or digital signals representative of the voltage at sensingpoint 32. The first voltage supply unit 44 can adjust the first supplyvoltage Vcc 45 provided to the integrated circuit 20 in order tocompensate form voltage drops.

FIG. 5 is a schematic electric diagram of two compensation circuits 90and 90′, a selection circuit 36 and various equivalent componentsaccording to an embodiment of the invention.

Conveniently, voltage drops at each of the sensing point 32 and 32′ canbe independently compensated by a compensation circuit (such as circuits90 and 90′) and, alternatively or additionally by a feedback path thatcan cause the first voltage supply unit 44 to adjust the first supplyvoltage Vcc.

According to an embodiment of the invention the feedback path can sendsampled voltages (or signals representative of the sampled voltages)from sensing points 32 and 32′ to the first voltage supply unit 44.According to another embodiment of the invention only a subset of thesampled voltages is sent to the first voltage supply unit 44. Thissubset is selected by a selection unit 36.

FIG. 5 illustrates various components such as compensation circuit 90,compensation circuit 90′, selection unit 36, pins 61 and 62 and firstand second voltage supply units 44 and 48. FIG. 5 also illustratesequivalent components that represent the resistance (represented byresistors 53, 63, 63′, 66 and 66′), capacitances (represented bycapacitors 52, 64 and 64′) and current consumption (represented bycurrent drains 65 and 65′) of various components as well as conductorsof the integrated circuit and various conductors connected to the firstand second voltage supply units 44 and 48.

Resistor 53 is connected between the first voltage supply unit 44 andpin 61. Capacitor 52 is connected between the ground and pin 61.Resistor 63 is connected between pin 61 and sensing point 32. Sensingpoint 32 is also connected to compensation circuit 90, to a first end ofcurrent drain 65, to a first end of resistor 66 and to a first end ofcapacitor 64. The other end of capacitor 64 and current drain 65 aregrounded.

Resistor 63′ is connected between pin 61 and sensing point 32′. Sensingpoint 32′ is also connected to compensation circuit 90′, to a first endof current drain 65′, to a first end of resistor 66′ and to a first endof capacitor 64′. The other end of capacitor 64′ and current drain 65′are grounded. Selection circuit 36 is connected to resistors 66 and 66′and to pin 63. Pin 63 is connected to the first supply voltage unit 44thus defining a feedback path 64.

The compensation circuits 90 and 90′ are connected via pin 62 to thesecond voltage supply unit 48. Compensation circuit 90 can be analoguesto compensation circuit 90′, although it can differ by its timeoutperiod as well as by the inclusion of a timeout circuit 78.

The output of peak detector 70 is connected to an input of timeoutcircuit 78. The output of timeout circuit 78 is connected to aninverting input 83 of comparator 80. The output 85 of comparator 80 isconnected to a gate of PMOS 92 so that it opens PMOS 92 when a voltagedrop is detected. The source of PMOS 92 is connected, via resistor 93and pin 62 to the second supply unit 48.

Typical (for a modern VLSI integrated circuit) non-limiting values ofresistor 53 are 0.01-0.1 Ohm, of resistor 63 (and of resistor 63′) are0.1-10 Ohm, of resistor 66 (and resistor 66′) ar10-1000 Ohm, ofcapacitor 52 are 100 pF-100 μF, of capacitor 64 (and capacitor 64′) are50 pF-1 nF, of current sink 65 (and of current sink 65′) are 1-500 mA.

FIG. 6 illustrates a peak detector 70 and a timeout circuit 78,according to an embodiment of the invention.

The peak detector includes diode 73 and capacitor 75 while the timeoutcircuit 78 includes capacitor 75 and resistor 77. The diode chargescapacitor 75. Once the capacitor 75 is charged by a peak voltage levelthe diode will not pass lower voltage levels. The timeout circuit 78 andespecially the resistor 77 provide a discharge path to capacitor 75.

Conveniently, the timeout period is responsive to the values ofcapacitor 75 and resistor 77. According to an embodiment of theinvention it is relatively fast in comparison to the speed of voltagescaling measures (such as DVFS). Conveniently the timeout expires oncethe feedback path and the first voltage supply unit 44 alter the firstsupply voltage in response to the voltage drop at sensing point 32.

FIG. 7 illustrates a voltage sampling circuit 30, according to anembodiment of the invention.

The voltage sampling unit 30 conveniently includes a selection circuit36 that receives multiple signals from multiple measurement (orsampling) points and selects a subset of signals to be provided to thevoltage supply unit 44. The selection reduces the amount of outputtedsignals and accordingly reduced the number of integrated circuit pinsthat should be allocated for outputting signals representative of thesampled voltages. It is further noted that time based multiplexing canalso be used in order to reduce the amount of utilized integrate circuitpins.

Conveniently, only a single integrated circuit pin (such as pin 63 ofFIG. 4) is used for outputting signal(s) representative of the sampledvoltage but this is not necessarily so.

According to other embodiments of the invention the amount of integratedpins used for outputting the voltage can differ then one.

The inventors used an analog voltage sampling circuit 30 that includedan analog selection circuit 36. Circuit 30 elects between multiplesampled voltages in an analog manner and outputs an analog output signalrepresentative of at least one of the sampled voltages. Circuit 30 maybe relatively simple and also sensitive to small voltage differencesthat can be a small fraction of the supply voltage. The inventors used acircuit that was sensitive to one percent of the supply voltage level.

The voltage sampling circuit 30 includes multiple sensing points (suchas points 32 and 32′), conductors 34 that are connected to these points,and selection circuit 36 that selects a subset out of the sampledvoltages to be outputted from the integrated circuit 20. Conveniently asingle sampled voltage is selected.

Conveniently the voltage sampling circuit 30 consumes a negligibleamount of energy and thus the voltage drop across the sampling circuitconductors (66 and 66′) is also negligible. Thus, the sensing points canbe located at any distance from the selection circuit 36 withoutsubstantially affecting the selection.

The voltage sampling circuit 30 outputs one or more signalsrepresentative of one or more sampled voltages. Conveniently, a singleanalog signal (such as the lowest voltage and/or the most significantvoltage) is sent to the voltage supply unit 44. The voltage supply unit44 then adjusts the outputted voltage in response to that (one or more)sampled voltage.

The exemplary voltage sampling circuit 30 includes multiple sensingpoints 32 that are connected via conductors 34 to selection circuit 36that includes multiple diodes (active or passive) 38 and pull-upresistor 39.

The diodes 38 are connected between different conductors 34 and anoutput node 37. A pull up resistor 39 is connected between the outputnode 37 and a voltage source that provides a working point to thediodes. In case of positive voltage supply the anode of each diode isconnected to a conductor while the cathodes of all diodes are connectedto an output node 37 of the selection circuit 36. The pull-up resistor36 is also connected between the output node 37 and a voltage sourceproviding a voltage bias for correct circuit operation.

The lowest voltage is provided, by one of diodes to the output node 37and causes the other diodes to receive a reverse bias voltage and tostop conducting.

If the selection circuit 36 should output multiple sampled voltages thanthe selection circuit 36 should include multiple output nodes.

FIG. 8 illustrates voltage drop and the result of two voltage dropcompensation measures, according to an embodiment of the invention.

The various curves were simulated by the inventors are reflect onlycertain curves out of many possible curves. Curve 206 illustrates anexemplary voltage drop. This voltage drop is not compensated by anymeans. A voltage drop begins at time T=0. The voltage at sensing point32 drops to about 1.75 nanoSeconds to about 1.165 Volts and stabilizesat a level of about 1.15 Volts after few tenths of nanoSeconds.

Curve 204 illustrates the behavior of the voltage at sensing point 32when a PMOS with the equivalent impedance of about 50 Ohm in the “ON”state is used as switch 92. The second supply unit voltage is chosenequal to 2.5V. After about 1.75 Nanoseconds (characterizing the responseperiod of the fast compensating circuit) the voltage reduction slowsdown and the voltage stabilizes at a level of about 1.162 Volts afterabout 5 Nano-Seconds.

Curve 202 illustrates the behavior of the voltage at sensing point 32when a PMOS with the equivalent impedance of about 20 Ohm in the “ON”state is used as switch 92. After about 1.75 Nanoseconds the voltagereduction ends and the voltage rises to a level of about 1.17 Voltsafter about 5 Nano-Seconds.

FIG. 9 is a flow chart of a method 100 for compensating for voltagedrops according to an embodiment of the invention.

Method 100 starts by stage 110 of providing at least a first supplyvoltage to an integrated circuit. Conveniently, a first supply voltageis supplied by a first voltage supply unit and a second supply voltageis supplied by a second voltage supply unit. The second supply voltageis conveniently higher than the first supply voltage.

Stage 110 is followed by stage 120 of detecting a voltage peak level ata sensing point. It is noted that the detection can occur before stage110, after stage 110, during stage 110 and the like. The detecting canoccur within a predefined measurement period, as well as within adynamically changing measurement period. The inventors utilized asliding window mechanism in which the voltage peak level was constantlymeasured. It is noted that the voltage peak level can be detected bysampling but this is not necessarily so.

Stage 120 is followed by stage 130 of comparing between a voltage levelat a sensing point within an integrated circuit to a reference voltagederived from a voltage peak level at the sensing point. Conveniently,the voltage peak level is measured during a peak measurement period.

Stage 130 is followed by stage 140 of selectively increasing the voltageat the sensing point in response to the comparison. When a voltage dropis detected (for example when the voltage level at a sensing point islower than the voltage peak level or when the voltage level at a sensingpoint is lower than the voltage peak level by more than a predefinedthreshold) the voltage is increased.

Conveniently, the voltage increment occurs by draining a current fromthe second voltage supply unit and charging at least one capacitor orcapacitance that is discharged as a result of the voltage drop.

Conveniently the voltage can be increased until the voltage levelsubstantially reaches the peak level.

Stage 140 is followed by stage 150 of reducing the reference voltage.This reduction stops the voltage increment after a timeout periodexpires. It is noted that the voltage increment can be stopped byupdating the voltage peak level, by shutting down a switch that providescurrent to the sensing point and the like.

FIG. 10 is a flow chart of a method 102 for compensating for voltagedrops according to an embodiment of the invention.

Method 102 differs from method 100 by including additional stages160-180. These stages can be executed in parallel to at least one stageout of stages 120-150, after one of these stages and the like.

Stage 160 includes sampling multiple sampled voltages (at multiplesensing points) and selecting a subset of the sampled voltages to beoutputted to a first voltage supply unit.

Stage 160 is followed by stage 170 of providing at least one sampledvoltage from at least one sensing point to the first voltage supplyunit.

Stage 170 is followed by stage 180 of adjusting a first supply voltageprovided to the integrated circuit in response to at least one sample.Stage 180 is followed by stage 110.

According to various embodiments of the invention method 102 can includea stage of sampling a single sampled voltage and providing it to thefirst voltage supply unit. According to other embodiments method 102does not include selecting a subset but rather all the sampled voltagesare provided to the first voltage supply unit.

According to other embodiments of the invention method 100 and 102 canbe used to compensate for voltage drops that occur at multiple sensingpoints. Conveniently each sensing point is managed independently toother sensing points.

According to an embodiment of the invention stage 150 ends after stage180 starts or even shortly after stage 180 starts. Thus, the adjustedfirst voltage supply voltage is provided to the integrated circuit afterthe compensation session of stages 130-140 ends. It is noted that theadjustment of the first supply voltage can occur at least in a partialoverlapping manner with the applying of stages 130 and 140.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

We claim:
 1. A method for compensating for voltage drops in anintegrated circuit, the method comprises: providing at least a firstsupply voltage to an integrated circuit; comparing a voltage level at asensing point within an integrated circuit to a reference voltagederived from a voltage peak level at the sensing point; and selectivelyincreasing the voltage at the sensing point in response to thecomparison.
 2. The method according to claim 1 further comprisingreducing the reference voltage.
 3. A method for compensating for voltagedrops in an integrated circuit, the method comprises: providing at leasta first supply voltage to an integrated circuit; comparing a voltagelevel at a sensing point within an integrated circuit to a referencevoltage derived from a voltage peak level at the sensing point; andselectively increasing the voltage at the sensing point in response tothe comparison, wherein the increasing comprises providing a currentfrom a second voltage supply unit.
 4. The method according to claim 1,further comprising detecting a voltage peak level at a sensing point. 5.The method according to claim 1, further comprising stopping theselectively increasing of the voltage after a timeout period expires. 6.The method according to claim 1, wherein the comparing comprisescomparing between a voltage level at multiple sensing points within anintegrated circuit to a multiple corresponding reference voltage derivedfrom a voltage peak level at the multiple sensing points; and whereinthe selectively increasing comprises selectively increasing a voltage ata sensing point in response to a comparison between the voltage leveland the reference voltage at that sensing point.
 7. The method accordingto claim 1, further comprising adjusting a first supply voltage providedto the integrated circuit in response to at least one voltage level ofat least one sensing point.
 8. The method according to claim 7 whereinthe increasing ends shortly after the adjusting begins.
 9. The methodaccording to claim 7 wherein the increasing at least partially overlapswith the adjusting.
 10. The method according to claim 7 wherein theadjusting is preceded by sampling multiple sensing points to providemultiple sampled voltages and selecting a subset of the sampled voltagesto be outputted to the first voltage supply unit.
 11. A devicecomprising: at least one current consuming component; and a compensationcircuit adapted to compare between a voltage level at a sensing pointwithin an integrated circuit and a reference voltage derived from avoltage peak level at the sensing point and to selectively increase thevoltage at the sensing point in response to the comparison.
 12. Thedevice according to claim 11 wherein the compensation circuit is adaptedto reduce the reference voltage.
 13. The device according to claim 11,wherein the compensation circuit is adapted to increase the voltage byproviding a current from a second voltage supply unit.
 14. The deviceaccording to claim 11, wherein compensation circuit comprises a peakdetector.
 15. The device according to claim 11, wherein compensationcircuit is adapted to stop the selectively increment of the voltageafter a timeout period expires.
 16. The device according to claim 11,further comprising additional compensation circuits that are adapted tocompensate for voltage drops at multiple sensing points.
 17. The deviceaccording to claim 11, further comprising a sampling circuit adapted tosend at least one sampled voltage to a first voltage supply unit. 18.The device according to claim 11, further comprising a selecting circuitadapted to select a subset of sampled voltages to be sent to the firstvoltage supply unit.
 19. The device according to claim 11, wherein thecompensation circuit comprises an I/O type transistor that is adapted toprovide a current to the sensing point.
 20. The device according toclaim 12, wherein the compensation circuit is adapted to increase thevoltage by providing a current from a second voltage supply unit.